View IR1175_299403.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Data Sheet PD 60178-D
IR1175
Synchronous Rectifier Driver
Features
n Provides constant and proper gate drive to power MOSFETs regardless of transformer output n Minimizes loss due to power MOSFET body drain diode conduction n Stand alone operation - no ties to primary side n Schmitt trigger input with double pulse suppression allows operation in noisy environments n High peak current drive capability - 2A n High speed operation - 2MHz n Adaptable to multiple topologies (such as singleended forward, double-ended forward)
Product Summary
Vdd IO+/- (peak) Fmax Max lead time 5Vdc 2A/2A 2MHz 500nsec
Description
The IR1175 is a high speed CMOS controller designed to drive N-channel power MOSFETs used as synchronous rectifiers in high current, high frequency forward converters with output voltages equal or below 5VDC. Schmitt trigger inputs with double pulse suppression allow the controller to operate in noisy environments. The circuit does not require any ties to the primary side and derives its operating power directly from the secondary. The circuit functions by anticipating transformer output transitions, then turns the power MOSFETs on or off before the transitions of the transformer to minimize body drain diode conduction and reduce associated losses. Turn on/off lead time can be adjusted to accommodate a variety of power MOSFET sizes and circuit conditions. The IR1175 also provides gate drive overlap/dead-time control via external components to further minimize diode conduction by nulling effects of secondary loop and device package inductance.
Packages
IR1175S
20 Lead Surface Mount (SSOP-20)
IR1175SS
20 Lead SOIC (MS-013AC)
IR1175
20 Lead PDIP (MS-001AD)
IR1175
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
Symbol
Vdd Iin PD RthJC RthJA TJ TS TL
Definition
Supply voltage Input clamp current Power dissipation (SSOP-20) Thermal resistance (SSOP-20) junction-to-case Thermal resistance (SSOP-20) junction-to-ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-- -- -- -- -- -- -55 --
Max.
7 +/- 10 400 28.5 90.5 150 150 300
Units
VDC mA DC mW C/W C/W C C C
Recommended Operating Conditions
Symbol
Vdd TA Freq Rbias UV Xin Cd1/Cd2
Definition
Supply voltage operating range Ambient temperature Operating frequency Required bias resistor (+/- 1%) Voltage at UVSET pin Maximum voltage at X1 and X2 inputs Capacitance at pins DTIN1 and DTIN2
Min.
-- -40 250 -- 1.75 -- --
Typ.
5 -- -- 69.8 -- -- --
Max.
-- 85 500 -- 2.25 5.6 22
Units VDC
C KHz K VDC VDC pF
2
www.irf.com
IR1175
Dynamic Electrical Characteristics
Vdd=5V, TA = 25 o C, Rbias = 69.8K unless otherwise specified.
Symbol
Vdd Iqdd Freq UVSET+ UVSETVxth+ VxthTadv Td Isink (peak) Isource (peak) VOH VOL tio
Definition
Supply voltage operating range Vdd quiescent current (Vin=0 or 5V, Iout=0) Operating frequency UVSET positive going threshold UVSET negative going threshold X1/X2 Input positive going threshold X1/X2 Input negative going threshold Externally adjustable lead time (advance) Externally adjustable dead-time for Q1 and Q2 Q1,Q2 output sink current (Vdd=5.0V, pulsed, 10 usec) Q1,Q2 output source current (Vdd=5.0V, pulsed, 10 usec) Q1, Q2 High level voltage (Iout = 20mA) Q1, Q2 Low level voltage (Iout = 20mA) Input to output delay (PLL bypassed, cross coupled mode)
Min.
4.0 -- 100 1.10 0.8 -- -- -- 20 --
Typ.
-- 3 -- -- -- 1.4 1.0 -- -- --
Max.
5.5 5 2000 1.4 1.1 -- -- 500 -- 2
Units
VDC mA DC KHz V V VDC VDC nsec nsec A
--
--
2
A
-- -- --
4.50 1.15 20
-- -- --
V nsec
tr tf Vtr
Gate turn-on rise time (C1=1000pf, Vdd=5V) Gate turn-off fall time (C1=1000pf, Vdd=5V) Cross-over voltage (Vdd=5Vdc, DTIN shorted to DTOUT, C1=1000pf) Fig. 3
-- -- --
20 20 2.5
-- -- --
nsec nsec VDC K VDC nsec A DC VDC KHz/ Volt
Rbias Vbias Tjitter Ichgpump Vchgpump Kvco_dc
Required bias resistor Voltage at Rbias pin Phase-lock loop output jitter Charge pump output current (at VFLTR pin) Charge pump output voltage (at VFLTR pin) PLL Vco DC gain
68 -- -20 -- 1.3 --
-- 1.25 -- 50 1.5 62
71 -- 20 -- 1.7 --
www.irf.com
3
IR1175
Lead Definitions and Assignments
Symbol Description
AVDD Q1 DTIN1 RADV1 VFLTR1 RVCO1 X1 VDD UVSET RBIAS AVSS X2 RVCO2 VFLTR2 RADV2 DTIN2 VSS Q2 Power - + 5 VDC to MOSFET drivers Output - gate drive for Q1 power MOSFET Input - sets dead time for Q1 - used with DTOUT1 Output - sets lead time (advance) for Q1 Output - PLL loop filter for Q1 output Output - sets PLL center frequency for Q1 output Input - transformer input for Q1 Power - +5 Vdc for internal logic Input - sets UVLO+ If this pin is pulled below 1.25VDC externally, then both Q1 and Q2 outputs will be at Vss (disabled) Output - connected to 69.8K +/- 1% resistor - sets operating current Ground for logic supply (AVDD) Input - transformer input for Q2 Output - sets PLL center frequency for Q2 output Output - PLL loop filter for Q2 Output - sets lead time (advance) for Q2 Input - sets dead time for Q2 - used with DTOUT2 Ground for MOSFET driver supply (VDD) Output - gate drive for Q2 power MOSFET
DTOUT1 Output - sets dead time for Q1 output - used with DTIN1
DTOUT2 Output - sets dead time for Q2 - used with DTIN2
1 *VDD 2 Q1 3 DTOUT2 4 DTIN2 5 RADV1 6 VFLTRI 7 RVCO1 8 X1 9 AVDD 10 UVSET
20 VSS 19 DTOUT1 18 DTIN1 17 RADV2 16 VFLTR2 15 RVCO2 14 X2 13 AVSS 12 RBIAS 11
Q2
1 *VDD 2 Q1 3 DTOUT2 4 DTIN2 5 RADV1 6 VFLTRI 7 RVCO1 8 X1 9 AVDD 10 UVSET
Q2 VSS DTOUT1 DTIN1 RADV2 VFLTR2 RVCO2 X2 AVSS RBIAS
20 19 18 17 16 15 14 13 12 11
1 *VDD 2 Q1 3 DTOUT2 4 DTIN2 5 RADV1 6 VFLTRI 7 RVCO1 8 X1 9 AVDD 10 UVSET
20 19 DTOUT1 18 DTIN1 17 RADV2 16 VFLTR2 15 RVCO2 14 X2 13 AVSS 12 RBIAS 11
Q2 VSS
IR1175S
(SSOP-20) 4
IR1175SS
SOIC (wide body)
IR1175
PDIP www.irf.com
IR1175
Fig. 1 Typical application circuit when supply Vout < 5.0 VDC
Fig. 2 Typical application circuit when supply Vout = 5.0 VDC www.irf.com 5
IR1175
Fig. 3 Gate drive characteristics and definitions
Phase Lock Loop Design Equations:
1 - Resistor to set VCO Ceter Frequency: Rvco (K) = 143 x [Vchgpump(VDC) / fvco(KHz)] x Kvco _ dc(KHz/Volt) Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz Rvco = 143 x [1.5 /300] x 62 Hz/Volt = 44.33 K 2 - Small Signal gain for VCO: Kvco_ac (KHz/Volt) = 1E3 x Kvco_dc (KHz/Volt)/(7 x Rvco(K) Example (B): Choosing same conditions as in example A: Kvco_ac = 1E3 x 62 / (7 x 44.33) = 199.9 KHz/volt
6
www.irf.com
IR1175
3 -PLL Nat r lf e u n y ua rqec:
n =2fn(KHz)= Ichpump(uA) x Kvco_ac(KHz/V) / C(nF)
Choose Cfs c t a Cf=C/16 uh ht 4 -PLL Dampi fc o c l u a i n : ng a t r a c l t o s
P = E-3 x Rf (KOhms) x C(nF) x fn(KHz)
Typi a v l ef rPi 0 7 7 ( r t c l yd mped) cl au o s .0. Ciial a 5 -Advance ti i m ng:
Tadv(nsec) = RADV (KOhms)*10 - 10
W here RADV i r s s a c f o RADV1 orRADV2 to ground. s eitne rm Exampl C:RADV=10Kohms wilr ti Tadv=10*10-10 =90 nsec . e l esul n 6-Dead tme cal u a i n : i cltos
Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V)
W here Rdt is resistance between pins DTIN1 and DTOUT1 or DTIN2 and DTOUT2.Cdti c p c t n ef o DTI or DTI t ground. s aaiac rm N1 N2 o Exampl D:Rdt=10Kohm s and Cdt=22pF wilr ti Td=156.8 nsec e l esul n:
Fig. 4 PLL loop filter component definitions
www.irf.com
7
IR1175
Fig. 5 IR1175 Block Diagram 8 www.irf.com
IR1175
Case Outline
20 Lead Surface Mount (SSOP-20)
01-6057 00 01-3078 00 (MS013AC)
www.irf.com
9
IR1175
Case Outline
20 Lead SOIC
01-6070 00 01-3080 00 (MS013AC)
10
www.irf.com
IR1175
Case Outline
20 Lead PDIP
01-6069 00 01-3079 00 (MS001AD)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 1/7/2002
www.irf.com
11

▲Up To Search▲

Price & Availability of IR1175

	To Download IR1175 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .